Alvin R. Lebeck


Alvin R. Lebeck
Professor of Computer Science
Professor of Electrical and Computer Engineering

Publications

  1. Accelerating Markov Random Field Inference using Molecular Optical Gibbs Sampling Units, Siyang Wang, Xiangyu Zhang, Yuxuan Li, Ramin Bashizade, Song Yang, Chris Dwyer, Alvin R. Lebeck, Proceedings of the 43rd International Symposium on Computer Architecture (ISCA), pages 558-569, June 2016.

  2. Combined Compute and Storage: Configurable Memristor Arrays to Accelerate Search, Yang Liu, Chris Dwyer, Alvin R. Lebeck, arXiv:1601.05273, Jan 2016 (From Yang Liu's Ph.D. Thesis in 2012).

  3. Exploiting Accelerators for Efficient High Dimensional Similarity Search, Sandeep R. Agrawal, Chris R. Dee, Alvin R. Lebeck, Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), March 2016.

  4. Nanoscale Resonance Energy Transfer-Based Devices for Probabilistic Computing, Siyang Wang, Alvin R. Lebeck, Chris Dwyer, IEEE Micro.35(5): pages 72-84, Sept/Oct 2015.

  5. More is Less, Less is More: Molecular-scale Photonic NoC Power Topologies, Jun Pang, Chris Dwyer, Alvin R. Lebeck, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 283- 296, March 2015.

  6. mNoC: Large Nanophotonic Network-on-Chip Crossbars with Molecular Scale Devices, Jun Pang, Chris Dwyer, Alvin R. Lebeck, ACM Journal on Emerging Technologies in Computing Systems.12(1), pages 1-25, July 2015.

  7. Rhythm: Harnessing Data Parallel Hardware for Server Workloads, Sandeep R. Agrawal, Valentin Pistol, Jun Pang, John Tran, David Tarjan, Alvin R. Lebeck, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 19-34, March 2014.

  8. Modeling and Simulation of a Nanoscale Optical Computing System, Jun Pang, Chris Dwyer, Alvin R. Lebeck, Journal of Parallel and Distributed Computing.74(6): pages 2470-2483, 2014.

  9. Exploiting Emerging Technologies for Nanoscale Photonic Networks-on-Chip, Jun Pang, Chris Dwyer, Alvin R. Lebeck, Sixth International Workshop on Network on Chip Architectures (NoCArc-13), pages 53-58, 2013 (Best Paper Award).

  10. Address Translation-Aware Memory Consistency, Bogdan F. Romanescu, Alvin R. Lebeck, and Daniel J. Sorin. in IEEE MICRO Top Picks from Computer Architecture Conferences of 2010, Volume 31, Issue 1, pages 109-118, January/February 2011.

  11. Fractal Consistency: Architecting the Memory System to Facilitate Verification , M. Zhang, A. R. Lebeck, D. J. Sorin, in Computer Architecture Letters, Volume 9, Issue 2, pages 61-64.

  12. Fractal Coherence: Scalably Verifiable Cache Coherence, M. Zhang, A. R. Lebeck, D. J. Sorin, in Proceedings of the 43rd International Symposium on Microarchitecture (MICRO), pages 471-482, December 2010.

  13. Encoded Multi-Chromophore Response for Simultaneous Label-Free Detection, C. Pistol, V. Mao, A. R. Lebeck, C. Dwyer. in Small Volume 6, No. 7, pages 843-850, April 9 2010.

  14. Specifying and Dynamically Verifying Address Translation-Aware Memory Consistency, Bogdan F. Romanescu, Alvin R. Lebeck, and Daniel J. Sorin. In Proceedings of the Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), pages 323-334, March 2010.

  15. Routing in Self-Organizing Nano-Scale Irregular Networks, Y. Liu, C. Dwyer, A. R. Lebeck, In ACM Journal on Emerging Technologies in Computing (JETC), pages 1-21, March 2010.

  16. Architectural Implications of Nanoscale Integrated Sensing and Computing, C. Pistol, W. Chongchitmate, C. Dwyer, A. R. Lebeck in IEEE MICRO Top Picks from Computer Architecture Conferences of 2009, 30(1), pages 110-120, January/February 2010.

  17. UNified Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All , B. F. Romanescu, A. R. Lebeck, D. J. Sorin, and A. Bracy. In 16th IEEE International Symposium on High-Performance Computer Architecture, January 2010.

  18. Nano-scale On-chip Irregular Network Analysis, Y. Liu, A. R. Lebeck, Proceedings of ICCCN 09 Workshop on Nano Molecular and Quantum Information Networks (NanoCom), August 2009.

  19. Architectural Implications of Nanoscale Integrated Sensing and Computing, C. Pistol, W. Chongchitmate, C. Dwyer, A. R. Lebeck, Proceedings of the Fourteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '09), pages 13-24, March 2009. (note: W. Chongchitmate was erroneously omitted as a co-author in the proceedings.)

  20. Nanoscale Optical Computing using Resonance Energy Transfer Logic, C. Pistol, C. Dwyer, A. R. Lebeck, IEEE MICRO, pages 7-18, November/December, 2008.

  21. Self-Assembled Computer Architecture, C. Dwyer and A. R. Lebeck, (Invited chapter), Systems Self-Assembly: multidisciplinary snapshots, eds. N. Krasnogor, et al. Elsevier, 2008

  22. An Introduction to DNA Self-assembled Computer Design, C. Dwyer, A. R. Lebeck, Artech House Publishers, 2008.

  23. A Defect Tolerant Self-organizing Nanoscale SIMD Architecture, J. Patwardhan, V. Johri, C. Dwyer, A. R. Lebeck, in ACM Journal on Emerging Technologies in Computing (JETC), Volume 3, No. 2, July 2007.

  24. Self-Organizing Defect Tolerant, Self-Assembled Nanoscale Architectures, A. R. Lebeck, C. Dwyer, in Nanoelectronic Devices for Defense and Security Conference, June 2007.

  25. Energy Transfer Logic on DNA Nanostructures: Enabling Molecular-Scale Amorphous Computing, C. Dwyer, A. R. Lebeck, C. Pistol, in Proceedings of the 4th Workshop on Non-Silicon Computing, pages 33-40, June 2007

  26. A Defect Tolerant Self-organizing Nanoscale SIMD Architecture, J. Patwardhan, V. Johri, C. Dwyer, A. R. Lebeck, in Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII), October 2006.

  27. Self-Assembled Networks: Control vs. Complexity, Jaidev Patwardhan, Chris Dwyer, Alvin R. Lebeck. 1st International Conference on Nano-Networks (NANONETS), September 2006.

  28. Design and Evaluation of Fail-Stop Self-Assembled Nanoscale Processing Elements, J. Patwardhan, C. Dwyer, A. R. Lebeck, in IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH '06), June 2006.

  29. Design Automation for DNA Self-Assembled Nanostructures, C. Pistol, C. Dwyer, A. R. Lebeck, in Proceedings of the 43rd Design Automation Conference (DAC), July, 2006.

  30. NANA: A Nano-scale Active Network Architecture, J. Patwardhan, C. Dwyer, A. R. Lebeck, D. J. Sorin, ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 2, No. 1, Pages 1-30, January 2006.

  31. Spin Detection Hardware for Improved Management of Multithreaded System, T. Li, A. R. Lebeck, D. J. Sorin, IEEE Transactions on Parallel and Distributed Systems, Volume 17, No. 6, June 2006.

  32. Finite-size, Fully-Addressable DNA Tile Lattices Formed by Hierarchical Assembly Procedures, S. H. Park, C. Pistol, S. J. Ahn, J. H. Reif, A. R. Lebeck, C. Dwyer, T. H. LaBean, Angewandte Chemie, Volume 45, Issue 5, Pages: 735-739, January 23, 2006.

  33. Evaluating the Connectivity of Self-Assembled Networks of Nano-scale Processing Elements, Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin, in IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH '05), May 2005.

  34. The Design and Fabrication of a Fully Addressable 8-tile DNA Lattice, Chris Dwyer, Sung Ha Park, Thom LaBean, Alvin R. Lebeck, Proceedings of the Foundations of Nanoscience: Self-Assembled Architectures and Devices (FNANO), April 2005

  35. Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution, Tong Li, Carla S. Ellis, Alvin R. Lebeck, and Daniel J. Sorin, in Proceedings of the USENIX Annual Technical Conference, April 2005.

  36. Experiences in Managing Energy with ECOSystem, H. Zengh, C. S. Ellis, A. R. Lebeck, IEEE Pervasive Computing, Volume 4, Issue 1, pages 62 - 68, Jan.-March 2005.

  37. Self-Assembled Architectures and the Temporal Aspects of Computing, Chris Dwyer, Alvin R. Lebeck, and Daniel J. Sorin, in IEEE Computer, 38 (1), pages 56-64, January 2005.

  38. Tolerating Memory Latency through Push Prefetching for Pointer-Intensive Applications, C. Yang, A. R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee, in ACM Transactions on Architecture and Code Optimization (ACM TACO), 1 (4), pages 445 - 475, Decmeber 2004.

  39. Design Tools for Self-assembling Nanoscale Technology, C. Dwyer, V. Johri, J. P. Patwardhan, A. R. Lebeck, and D. J. Sorin, in Institute of Physics Nanotechnology 15 (9) pages 1240-1245, September 2004.

  40. Circuit and System Architecture for DNA-Guided Self-Assembly of Nanoelectronics, Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin, in Proceedings of the Foundations of Nanoscience: Self-Assembled Architectures and Devices (FNANO), April 2004

  41. Communication Breakdown: Analyzing CPU usage in Commercial Web Workloads, J. P. Patwardhan, A. R. Lebeck, D. J. Sorin in International Symposium on Performance Analysis of Systems and Software (ISPASS '04), March 2004.

  42. Exploiting Global Knowledge to Achieve Self-Tuned congestion Control for k-ary n-cube Networks, M. Thottethodi, A. R. Lebeck, S. Mukherjee, in IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), 15(3), pages 257-272, March 2004.

  43. The Synergy between Power-aware Memory Systems and Processor Voltage Scaling, X. Fan, C S. Ellis, A. R. Lebeck, in Power Aware Computer Systems (PACS'03), Springer-Verlag, December 2003.

  44. Quantifying Instruction Criticality for Shared Memory Multiprocessors, T. Li, A. R. Lebeck, D. J. Sorin, in Proceedings of the International Symposium on Parallelism in Algorithms and Architectures, June 2003.

  45. Currentcy: Unifying Policies for Resource Management, H. Zeng, C. Ellis, A. Lebeck, A. Vahdat, May 2002, in USENIX 2003, June 2003. (draft version)

  46. BLAM: A High-Performance Routing Algorithm for Virtual Cut-Through Networks, M. S. Thottethodi, A. R. Lebeck, S. Mukherjee, in Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), April 2003.

  47. ECOSystem: Managing Energy as a First Class Operating System Resource, H. Zeng, X. Fan, C. Ellis, A. R. Lebeck, and A. Vahdat, in Proceedings of the Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS X), October 2002.

  48. A Large, Fast Instruction Window for Tolerating Cache Misses, A. R. Lebeck, J. Koppanalil, T. Li, J. Patwardhan, E. Rotenberg, in Proceedings of the 29th International Symposium on Computer Architecture (ISCA), May 2002. Technical report with more data is here.

  49. A Programmable Memory Hierarchy for Prefetching Linked Data Structures, C. Yang, A. R. Lebeck, in Proceedings of the 4th International Symposium on High Performance Computing (ISHPC-IV), Springer-Verlag, May 2002, Japan.

  50. Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets, X. Fan, C. S. Ellis, A. R. Lebeck, in Proceedings of the Workshop on Power-Aware Computer Systems (PACS'02), Springer-Verlag, February,2002.

  51. Recursive Array Layouts and Fast Parallel Matrix Multiplication, S. Chatterjee, A. R. Lebeck, Praveen K. Patnala, M. Thottethodi, in IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), 2002.

  52. ECOSystem: Managing Energy as a First Class Operating System Resource, H. Zeng, X. Fan, C. Ellis, A. R. Lebeck, and A. Vahdat, Duke Computer Science technical report CS-2001-01, basis of poster presentation at SOSP 2001.

  53. Memory Controller Policies for DRAM Power Management, X. Fan, C. S. Ellis, A. R. Lebeck, in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED) August, 2001. ( ps)

  54. Locality vs. Criticality, S. Srinivasan, R. Ju, A. R. Lebeck, C. Wilkerson,  in Proceedings of the 28th International Symposium on Computer Architecture (ISCA), June 2001.

  55. Array Merging: A Technique for Improving Cache and TLB Behavior, D. Genius, S. Chatterjee, and A. R. Lebeck, in Workshop on Memory Performance Issues, June 2001.

  56. Exact Analysis of the Cache Behavior of Nested Loops, S. Chatterjee, E. Parker, P. Hanlon, A. R. Lebeck, in Proceedings of the International Symposium on Programming Language Design and Implementation (PLDI), June 2001. ( ps)

  57. Self-Tuned Congestion Control for Multiprocessor Networks, M. S. Thottethodi, A. R. Lebeck, S. Mukherjee,  in Proceedings of the Seventh International Symposium on High Performance Computer Architecture (HPCA-7), January 2001 ( ps)

  58. The Combinatorics of Cache Misses During Matrix Multiplication, P. J. Hanlon, D. Chung, S. Chatterjee, D. Genius, A. R. Lebeck, and E. Parker, in  Journal of Computer Sciences and Systems, 2001.

  59. Power Aware Page Allocation, Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla S. Ellis, in Proceedings of Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IX), November 2000.

  60. Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions, C. Yang, B. Sano, and A. R. Lebeck, In IEEE Transactions on Computers, 49(9), September 2000.

  61. Every Joule is Precious: The Case for Revisiting Operating System Design for Energy Efficiency, A. Vahdat, A. R. Lebeck, C. S. Ellis, 9th ACM SIGOPS European Workshop, September 2000.

  62. Push vs. Pull: Data Movement for Linked Data Structures, Chia-Lin Yang and Alvin R. Lebeck, International Conference on Supercomputing 2000 (ICS '00), May 2000.

  63. Load Latency Tolerance In Dynamically Scheduled Processors, Srikanth T. Srinivasan and Alvin R. Lebeck, Journal of Instruction-Level Parallelism (JILP), Volume 1, October 1999 ( http://www.jilp.org/vol1) (Invited Paper)

  64. Network I/O with Trapeze, Jeff Chase, Darrell Anderson, Andrew Gallatin, Alvin Lebeck, and Ken Yocum, 1999 Hot Interconnects Symposium, August 1999. (Invited Paper)

  65. Annotated Memory References: A Mechanism for Informed Cache Management , A. R. Lebeck, D. R. Raymond, C. Yang, M. S. Thottethodi, Euro-Par '99, August 1999. (Short Version)

  66. Recursive Array Layouts and Fast Matrix Multiplication, S. Chatterjee, A. R. Lebeck, P. K. Patnala, M. S. Thottethodi, 11th ACM Symposium on Parallel Algorithms and Architectures (SPAA '99), June 1999.

  67. Nonlinear Array Layouts for Hierarchical Memory Systems, S. Chatterjee, V. Jain, A. R. Lebeck, S. Mundhra, M. S. Thottethodi, 13th ACM International Conference on Supercomputing (ICS '99), June 1999.

  68. Cache Conscious Programming in Undergraduate Computer Science, Alvin R. Lebeck, ACM SIGCSE Technical Symposium on Computer Science Education (SIGCSE '99), March 1999.

  69. Load Latency Tolerance In Dynamically Scheduled Processors, Srikanth T. Srinivasan and Alvin R. Lebeck, ACM/IEEE International Symposium on Microarchitecture (MICRO), November 1998. Best paper award.

  70. Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications, Chia-Lin Yang, Barton Sano, and Alvin R. Lebeck, ACM/IEEE International Symposium on Microarchitecture (MICRO), November 1998

  71. Tuning Strassen's Matrix Multiplication for Memory Efficiency, Mithuna S. Thottethodi, Siddhartha Chatterjee, and Alvin R. Lebeck Supercomputing '98, November 1998 postscript (nominated for best student paper)

  72. Architecture-Efficient Strassen's Matrix Multiplication: A Case Study of Divide-and-Conquer Algorithms, V. P. Pauca, X. Sun, S. Chatterjee, and A. R. Lebeck, In International Linear Algebra Society (ILAS) Symposium on Algorithms for Control, Signals, and Image Processing, June 1997. Also Technical Report CS-1998-06 Department of Computer Science, Duke University, May 1998

  73. Cut-Through Delivery in Trapeze: An Exercise in Low-Latency Messaging, Ken Yocum, Jeff Chase, Andrew Gallain, and Alvin R. Lebeck, Proceedings of IEEE International Symposium on High Performance Distributed Computing (HPDC), August 1997 (postscript)

  74. Active Memory: A New Abstraction For Memory System Simulation, Alvin R. Lebeck and David A. Wood, ACM Transactions on Modeling and Computer Simulation, 7(1), pages 42-77, January 1997

  75. Tools and Techniques for Memory System Design and Analysis, Alvin R. Lebeck Ph.D. Dissertation November 1995

  76. Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors, Alvin R. Lebeck and David A. Wood, ACM/IEEE International Symposium on Computer Architecture (ISCA), June 1995

  77. Active Memory: A New Abstraction For Memory System Simulation, Alvin R. Lebeck and David A. Wood, ACM SIGMETRICS May 1995

  78. Application-Specific Protocols for User-Level Shared Memory, Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, Ioannis Schoinas, Mark D. Hill James R. Larus, Anne Rogers, and David A. Wood, Supercomputing '94, November 1994

  79. Fine-grain Access Control for Distributed Shared Memory, Ioannis Schoinas, Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, James R. Larus, and David A. Wood, The Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VI), Oct. 1994.

  80. Cache Profiling and the SPEC Benchmarks: A Case Study, Alvin R. Lebeck and David A. Wood, pages 15-26, IEEE COMPUTER, October 1994

  81. Request Combining in Multiprocessors with Arbitrary Interconnection Networks, Alvin R. Lebeck and Gurindar S. Sohi, IEEE TPDS, November 1994

  82. Mechanisms for Cooperative Shared Memory, David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, Steven K. Reinhardt, ACM/IEEE International Symposium on Computer Architecture (ISCA), May 1993.

  83. The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers, Steven K. Reinhardt, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, David A. Wood, ACM SIGMETRICS, May 1993.

  84. Inexpensive Implementations of Set-Associativity, Richard E. Kessler, Richard J. Jooss, Alvin R. Lebeck, Mark D. Hill, ACM/IEEE International Symposium on Computer Architecture (ISCA), pages 131-139, May 1989.